Data transfer control system, electronic apparatus, and program

ABSTRACT

A data transfer control system that controls data transfer between a first electronic apparatus connected via a first bus and a device connected via a second bus, including: a management section that conducts a process of receiving a login request when a login request for acquirement of a right to access to the device comes from the first electronic apparatus and that conducts a process of receiving a logout request when a logout request for abandonment of the access right acquired upon receipt of the login request comes from the first electronic apparatus; and a power control section that conducts power control by turning on power supply to the device when the login request to the device comes from the first electronic apparatus.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to a system, an electronic apparatus, anda program for data transfer control.

2. Related Art

In recent years, high-speed serial interfaces such as IEEE1394 andUSB2.0 are drawing much attention. In order to realize these high-speedserial interfaces, there are various conventional methods for reducingelectricity consumption of an electronic apparatus which incorporatestherein a data transfer control system.

However, in the conventional methods, the electricity consumption of theelectronic apparatus (a peripheral apparatus) incorporating the datatransfer control system is realized, for example, by detecting statusesof power supply in a host system such as a personal computer (PC).Further, not enough reduction of electricity consumption has beenrealized with devices such as a hard disc drive (HDD) contained in theelectronic apparatus.

Japanese Unexamined Patent Publication No. 11-212681 is an example ofrelated art.

SUMMARY

An advantage of the invention is to provide a system, an electronicapparatus, and a program for data transfer control which can realizepower control that can highly effectively reduce electricityconsumption.

The invention relates to a data transfer control system that controlsdata transfer between a first electronic apparatus connected via a firstbus and a device connected via a second bus, including: a managementsection that conducts a process of receiving a login request when alogin request for acquirement of a right to access to the device comesfrom the first electronic apparatus and that conducts a process ofreceiving a logout request when a logout request for abandonment of theaccess right acquired upon receipt of the login request comes from thefirst electronic apparatus; and a power control section that conductspower control by turning on power supply to the device when the loginrequest to the device comes from the first electronic apparatus.

In the invention, when the login/logout request for acquirementof/abandonment of the right to access to the device comes, the processof receiving the request is carried out. Then, when the login requestcomes in (when the login request is received), the power control iscarried out by turning on power supply to the device, and the datatransfer between the first electronic apparatus and the device isconducted. Consequently, the power supply to the device can stay turnedoff until the login request comes in, and the power control that canhighly effectively reduce electricity consumption can be realized.

Further, in the invention, the power control section may conduct powercontrol by turning off or saving power supply to the device when alogout request to the device comes from the first electronic apparatus.

As a consequence, after the logout request comes, the power supply tothe device can be turned off or saved, and unwanted electricityconsumption can be avoided at the device that stopped being used uponthe logout.

Furthermore, in the invention, the power control section may conductpower control by turning off or saving power supply to the device whenthe first bus turns non-biased or disconnected.

Additionally, in the invention, a first data transfer process betweenthe first electronic apparatus and the device may be switched to asecond data transfer process between the second electronic apparatus andthe device when the first bus is not in an active state and when powersupply of a power line of a third bus that is connected to a secondelectronic apparatus is in an on state.

Consequently, the switch from the first data transfer control process tothe second data transfer control process is possible by a simpledetermination process.

In addition, in the invention, the power control section may conductpower control by turning off power supply to a link layer circuit usedfor the first data transfer process when the first data transfer processis switched to the second data transfer process.

Moreover, in the invention, the second data transfer process may beswitched to the first data transfer process when the first bus is in anactive state and when power supply of the power line of the third bus isin an off state.

Consequently, the switch from the second data transfer control processto the first data transfer control process is possible by a simpledetermination process.

Further, in the invention, the power control section may conduct powercontrol by turning on power supply to a link layer circuit used for thefirst data transfer process when the second data transfer process isswitched to the first data transfer process.

Furthermore, the invention relates a data transfer control system thatcontrols data transfer between a first electronic apparatus connectedvia a first bus and a device connected via a second bus, including: amanagement section that conducts a process of receiving a login requestwhen a login request for acquirement of a right to access to the devicecomes from the first electronic apparatus and a process of receiving alogout request when a logout request for abandonment of the access rightacquired upon receipt of the login request comes from the firstelectronic apparatus; and a power control section that conducts powercontrol by turning off or saving power supply to the device when thelogout request to the device comes from the first electronic apparatus.

In the invention, when the login/logout request foracquirement/abandonment of the right to access to the device comes in,the process of receiving the request is carried out. Then, when thelogout request comes in (when the logout request is received), the powercontrol is conducted by turning off or saving power supply to thedevice. As a consequence, it is able to avoid unwanted electricityconsumption at the device that stopped being used upon the logout.

Further, the invention relates to an electronic apparatus including: thedata transfer system of any of the descriptions above; and the deviceconnected via the second bus.

Furthermore, the invention relates to the electronic apparatus, furtherincluding: a power switch that turns on or off power of an electronicapparatus; a power supply circuit that supplies power when the powerswitch is turned on; and a switch circuit, which receives a powercontrol signal for controlling power supply from the data transfercontrol system to the device, supplies power from the power supplycircuit to the device when the power control signal turns active, andturns off or saves power supply from the power supply circuit to thedevice when the power control signal turns inactive.

Moreover, the invention relates to a program that controls data transferbetween a first electronic apparatus connected via a first bus and adevice connected via a second bus, wherein the program makes a computerto carry out: a process of receiving a login request when a loginrequest for acquirement of a right to access to the device comes fromthe first electronic apparatus; a process of receiving a logout requestwhen a logout request for abandonment of the access right acquired uponreceipt of the login request comes from the first electronic apparatus;and power control by turning on power supply to the device when a loginrequest to the device comes from the first electronic apparatus.

Additionally, the invention relates to a program that controls datatransfer between a first electronic apparatus connected via a first busand a device connected via a second bus, wherein the program makes acomputer to carry out: a process of receiving a login request when alogin request for acquirement of a right to access to the device comesfrom the first electronic apparatus; a process of receiving a logoutrequest when a logout request for abandonment of the access rightacquired upon receipt of the login request comes from the firstelectronic apparatus; and power control by turning off or saving powersupply to the device when a logout request to the device comes from thefirst electronic apparatus.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described with reference to the accompanyingdrawings, wherein like numbers refer to like elements and wherein:

FIG. 1 is a diagram to explain an outline of a SBP-2 process.

FIG. 2 is a diagram to explain data transfer of the SBP-2 using an ORBincluding a write command.

FIG. 3 is a diagram to explain data transfer of the SBP-2 using an ORBincluding a read command.

FIGS. 4 A to 4C are diagrams to explain a login ORB, a logout ORB, andthe like.

FIG. 5 is an example configuration of a data transfer control system andan electronic apparatus of the embodiment.

FIG. 6 is another example configuration of the data transfer controlsystem and the electronic apparatus of the embodiment.

FIGS. 7A to 7C are diagrams to explain the technique of the embodiment.

FIGS. 8A to 8C are diagrams to explain the technique of the embodiment.

FIG. 9 is a flowchart illustrating a process of the embodiment.

FIG. 10 is a flowchart illustrating the process of the embodiment.

FIG. 11 is a flowchart illustrating the process of the embodiment.

DESCRIPTION OF THE EMBODIMENT

The embodiment of the invention will now be described. The embodimenthereinafter described will not unduly limit the content of the inventiondescribed in the claims. Further, not all the configurations explainedin the embodiment are indispensable aspects of the invention.

1.1 EEE1394, SBP-2

1.1 SBP-2

IEEE1394 protocols (e.g. IEEE1394-1995, P1394a, and P1394b) consist of atransaction layer, a link layer, and a physical layer. Further, aprotocol called Serial Bus Protocol-2 (SBP-2) has been proposed as anupper protocol that partially includes functions of the transactionlayer of IEEE1394 (to define broadly, a first interface standard). ThisSBP-2 (SBP) has been proposed so that an SCSI command set can be used onthe IEEE1394 protocol.

FIG. 1 is a flowchart illustrating an outline of a process of the SBP-2(broadly, an upper first protocol of the first interface standard). Withthe SBP-2, a read process of a configuration ROM is first conducted inorder to verify connection devices (step T1). Next, a login process isconducted (step T2) so that an initiator (an electronic apparatus or ahost system such as a personal computer) acquires the right to access(the right to use a bus) to a target (a device such as HDD). Morespecifically, the login process is carried out using a login operationrequest block (ORB) created by the initiator. Then, a fetch agent isinitiated (step T3). Thereafter, a command process is carried out (stepT4) using a command block ORB (a command packet), and, finally, a logoutprocess is carried out (step T5) using a logout ORB.

In the command process of the step T4 in FIG. 1, the initiator sends awrite request packet and rings a doorbell register of the target asshown at A1 in FIG. 2. Then, as shown at A2, the target sends a readrequest packet, and the initiator sends back a corresponding readresponse packet. Consequently, the ORB created by the initiator isfetched by a data buffer of the target, which then analyzes a commandincluded in the fetched ORB.

Then, if the command included in the ORB is a write command of SCSI, thetarget sends a read request packet to the initiator, which then sends acorresponding read response packet to the initiator as shown at A3.Consequently, data stored in the data buffer of the initiator is sent tothe target and written into a device (a storage device such as HDD) ofthe target.

In contrast, if the command included in the ORB is a read command ofSCSI, the target sends a series of write request packets to theinitiator as shown at B1 of FIG. 3. Consequently, data read out from thedevice is transferred to the data buffer of the initiator.

According to the SBP-2, the target is able to create a request packet(issues a transaction) at its own convenience and to send/receive thedata. Therefore, since there is no need for the initiator and the targetto operate in synchronization with each other, data transfer efficiencycan be increased.

Further, the login process in the step T2 of FIG. 1 can be conductedwhen the initiator sends the login ORB shown in FIG. 4A to the target,which then returns the login response packet shown in FIG. 4B to theinitiator. Also, the logout process of the step T5 in FIG. 1 can beconducted when the initiator sends the logout ORB shown in FIG. 4C tothe target.

2. General ConFIG.uration

FIG. 5 shows an example configuration of the data transfer controlsystem and the electronic apparatus including the same of theembodiment. It should be noted that, although the hard disc drive (HDD)is exemplified in the following descriptions as the device to becontained in the electronic apparatus which is the target, the inventionis not limited to the HDD. For example, the device contained in theelectronic apparatus may be any storage device other than the HDD, suchas an optical disc drive or a magnet-optical disc drive, or it may beany device other than such storage device. Further, although a personalcomputer (a PC) is exemplified in the following descriptions as thefirst electronic apparatus connected to the electronic apparatus via aBUS1, the invention is not limited thereto. For example, the firstelectronic apparatus may be any electronic apparatus other than the PC,such as a portable information-processing terminal or a cellular phone.Further, the BUS1 may be any high-speed serial bus (including amulti-channel serial bus) other than the IEEE1394 bus, and part of orthe entire BUS1 may be wireless.

A personal computer PC1 containing a data buffer 4 (to define broadly,the first electronic apparatus, or the first host system) and anelectronic apparatus 8 are connected by the BUS1 (the first bus, or thefirst serial bus) which complies with IEEE1394 or the like.

Further, the electronic apparatus 8 includes a data transfer controlsystem 10 and a device 100 (a single or plural logical units). Also, theelectronic apparatus 8 further includes: a power switch 110 for turningon/off power of the electronic apparatus 8 (the data transfer controlsystem 10), a power supply circuit 112 that supplies power when thepower switch 110 is turned on, and a switch circuit 114 that turns on oroff (or saves) power supply from the power supply circuit 112 to a HDD100 based on a power control signal PSC coming from the data transfercontrol system 10. In addition, although FIG. 5 shows a case in whichthere is one HDD which is a logical unit, there may be more than onelogical units. Also, the electronic apparatus 8 may contain a system CPU(not shown), a system memory (ROM or RAM), an operation section, adisplay section, and a signal processing device, for example.

The data transfer control system 10 includes a transfer controller 12, abuffer controller 38, a data buffer 40, and a processing section 50.Alternatively, some of these elements may be omitted. For example, thebuffer controller 38 and the data buffer 40 may be omitted.

The transfer controller 12 is a controller that controls the datatransfer between the PC1 (the first electronic apparatus) connected bythe BUS1 and the HDD 100 (the device) connected by the BUS2.

The buffer controller 38 is a controller that controls access (writeaccess and read access) to the data buffer 40 that temporarily storesthe transfer data. The buffer controller 38 contains a pointermanagement section 39. This pointer management section 39 controlspointers of the data buffer 40 by a ring buffer method and carries out aprocess of renewing a plurality of pointers for writing and reading.Further, the buffer controller 38 can contain a register that controlsthe buffer controller 38, an adjustment circuit that adjusts connectionof the bus to the data buffer 40, a sequencer that generates variouscontrol signals, and the like.

The data buffer 40 (a packet buffer) is a buffer (a storage) thattemporarily stores the transfer data (the packets) and is composed ofsuch hardware as an SRAM, a SDRAM, or a DRAM. Additionally, in theembodiment, the data buffer 40 can be accessed randomly. Also, the databuffer 40 may be installed outside the data transfer control system 10instead of inside thereof.

The transfer controller 12 contains a physical layer (PHY) circuit 14, alink layer (& transaction) circuit 20, an SBP-2 circuit 22, and aninterface circuit 30. The transfer controller 12 may not necessarilyinclude all the circuit blocks shown in FIG. 5 but may exclude some ofthem. For example, the physical layer (PHY) circuit 14 may be excluded.

The physical layer circuit 14 is a circuit to realize a physical layerprotocol by use of hardware and includes a function of inverting logicalsymbols used by the link layer circuit 20 into electric signals. Thelink layer circuit 20 is a circuit to realize part of the link layerprotocol or the transaction layer protocol by use of hardware andprovides various services for the packet transfers between nodes. Havingthese functions, the physical layer circuit 14 and the link layercircuit 20 make it possible to carry out the data transfer in compliancewith IEEE1394 between the data transfer control system 10 and the PC1via the BUS1.

The SPB-2 circuit 22 (to define broadly, a transfer executing circuit)is a circuit that carries out part of the SBP-2 protocol or of thetransaction layer by use of hardware. This function of the SBP-2 circuit22 makes it possible to divide the transfer data into a series ofpackets and to continuously transfer the series of divided packets.

The interface circuit 30 is a circuit that carries out an interfaceprocess between the data transfer control system 10 and the HDD 100 (todefine broadly, the device). This function of the interface circuit 30makes it possible to carry out the data transfer in compliance with anAT Attachment (ATA) and an ATA packet interface (ATAPI) between the datatransfer control system 10 and the HDD 100 via the BUS2.

In addition, the physical layer circuit 14, the link layer circuit 20,the interface circuit 30, and the like enable the data transfer controlsystem 10 to have the conversion bridge function of IEEE1394 (to definebroadly, the first interface standard) and of ATA (IDE)/ATAPI (broadly,the second interface standard).

A DMA controller 32 contained in the interface circuit 30 is a circuitthat carries out a direct memory access (DMA) transfer between the datatransfer control system 10 and the HDD 100 via the BUS2. Further, theHDD 100 connected by the BUS2 includes an interface circuit 102 thatcarries out the data transfer in compliance with ATA (IDE)/ATAPI, anaccess control circuit 104 that controls access (write-in or read-outcontrol) to a storage 106, and the storage 106 such as a hard disc.

The processing section 50 carries out control of the data transfer andcontrol of the whole apparatus. The processing section 50 includes acommunication section 52, a management section 60, a fetch section 70, atask section 80, and a power control section 90. Alternatively, some ofthese sections may be omitted. Each of these sections included in theprocessing section 50 can be operated by a program (firmware) thatoperates with a hardware circuit such as the CPU (the processor) on theCPU. This program (a process module) can be stored in an electricallyerasable and programmable read only memory (EEPROM) or a storage such asROM. Alternatively, some or all of these sections in the processingsection 50 may be operated by an application specific hardware circuit(ASIC).

The communication section 52 carries out an interface process betweenthe processing section 50 and the hardware circuits such as the physicallayer circuit 14 and the link layer circuit 20.

The management section 60 (a management agent) conducts managementprocesses such as login, reconnect, logout, and reset. For example, whena login request (a login ORB) for acquirement of the right to access tothe HDD (the device) comes from the PC1 (the first electronic apparatusor the initiator), the management section 60 conducts the process ofreceiving this login request at first. Also, when the logout request(the logout ORB) for abandonment of the access right acquired uponreceipt of the login request comes from the PC1, the management section60 conducts the process of receiving this logout request.

When the login request is received, the data transfer (a streamtransfer) between the PC1 connected via the BUS1 and the HDD 100connected via the BUS2 becomes possible. That is, the control of thetransfer controller 12 makes it possible to operate the data transferbetween the PC1 and the HDD 100. In contrast, when the logout request isreceived, the PC1 loses the right to access to the HDD 100, and the datatransfer between the PC1 and the HDD 100 stops.

The fetch section 70 (a fetch agent) carries out processes such asreceiving the operation request blocks (ORBs), issuing statuses, andrequesting commands to the task section 80. The fetch section 70 differsfrom the management section 60 which can only handle a single requestbut can handle linked lists of the ORBs that the fetch section 70 itselfhas fetched upon request from the initiator.

The task section 80 (a storage task section) processes the commandsincluded in the ORB and the DMA transfer. The task section 80 contains acommand processing section 82.

The command processing section 82 carries out various processespertaining to the ORB that is transferred via the BUS1 (the first bus ofthe first interface standard such as IEEE1394). More specifically, afterthe login request is accepted and when the command ORB (a commandpacket) from the PC1 is received, the data transfer between the datatransfer control system 10 and the HDD 100 connected via the BUS2 (thesecond bus of the second interface standard such as ATA/ATAPI) startsbased on the command (the command of SCSI or SPC-2) given by the ORB.Even more specifically, the command processing section 82 issues thecommand included in the ORB to the HDD 100 upon receipt of the ORB fromthe PC1 and starts the DMA transfer (the data transfer withoutinterference of the processing section) via the BUS2.

The power (and clock) control section 90 conducts various controlspertaining to the power (and clock) supply to the HDD 100 or the linklayer circuit 20 (the transfer controller 12). For example, when thelogin request to the HDD 100 comes from the PC1 (when the login requestis accepted), the power control section 90 conducts the power control byturning on the power supply to the HDD 100. More specifically, the powercontrol section 90 activates the power control signal PSC that controlsthe power supply to the HDD 100. Then, the switch circuit 14 that hasreceived this power control signal PSC supplies power from the powersupply circuit 112 to the HDD 100. As a consequence, because there willbe no power supplied from the power supply circuit 112 to the HDD 100until the login request comes, electricity consumption can be reduced.Then, when the login request comes, the HDD 100 is able to operateproperly on the power supplied from the power supply circuit 112.

In contrast, when a logout request to the HDD comes from the PC1 (when alogout request is received), the power control section 90 carries outthe power control by turning off (or saving) power supply to the HDD100. More specifically, the power control section 90 sets the powercontrol signal PSC inactive. Then, the switch circuit 114 that hasreceived this power control signal PSC turns off (or save) the powersupply from the power supply circuit 112 to the HDD 100. As aconsequence, when the PC1 loses the right to access to the HDD 100,which will then stop being used, the power supply to the HDD 100 can beturned off (or saved), and reduction of electricity consumption becomespossible.

FIG. 6 is another configuration example of the data transfer controlsystem and the electronic apparatus of the embodiment. In FIG. 6, theelectronic apparatus 8 contains a port 121 for the first bus BUS1 (forIEEE1394) and a port 122 for the third bus BUS3 (for the USB). Then, thedata transfer control system 10 (a first data transfer control IC)controls the data transfer (the first data transfer process) between thePC1 (the first electronic apparatus) connected via the BUS1 (the port121) and the HDD 100 connected via the BUS2. Further, a data transfercontrol system 11 (a second data transfer control IC) controls the datatransfer (the second data transfer process) between the PC2 (the secondelectronic apparatus) connected via the BUS3 (the port 122) and the HDD100 connected via the BUS2.

According to the configuration of FIG. 6, the PC2 can write in or readin data using the HDD 100 when the PC1 is not using the HDD 100. Morespecifically, when the BUS1 is not in an active state (the cable is notactive) and when the power supply of a VBUS (to define broadly, a powerline) of the BUS3 is turned on, the first data transfer process betweenthe PC1 and the HDD 100 is switched to the second data transfer processbetween the PC2 and the HDD 100. In contrast, when the PC2 is not usingthe HDD 100, the PC1 can write in or read in data using the HDD 100.More specifically, when the BUS1 is active and when the power supply ofthe VBUS of the BUS3 is turned off, the second data transfer processbetween the PC2 and the HDD 100 is switched to the first data transferprocess between the PC1 and the HDD 100.

3. Technique Used in the Embodiment

3.1 Power Linking Operation

Conventionally, when the power switch 110 of the electronic apparatus 8is on, the power supply to the HDD 100 also stays on. Therefore, afterthe power switch 110 is turned on and before the PC1 logs into the HDD100, electricity is being consumed at the HDD 100.

However, during a period before the PC1 logs into the HDD 100, the PC1does not have the right to access to the HDD 100, and the HDD 100 is notbeing in use. Thus, the electricity consumed at the HDD 100 during thisperiod is wasted.

Hence, in the embodiment, a power linking operation that controls thepower supply to the device (the HDD) is conducted depending on thelogin/logout status of IEEE1394 and the connected/disconnected status ofthe IEEE1394 cable. Further, in the case of the USB, the power linkingoperation that controls the power supply to the device is conducteddepending on the on/off status of the VBUS and theconnected/disconnected status of the USB cable.

More specifically, as shown in FIG. 7A, even when the power switch 110of the electronic apparatus 8 is turned on, the power supply to the HDD100 stays off. In other words, the power control section 90 sets thepower control signal PSC inactive, and, receiving this, the switchcircuit 114 turns off the power supply from the power supply circuit 112to the HDD 100.

Then, as shown in FIG. 7B, upon receiving the login request from thePC1, the power supply to the HDD 100 is turned on. More specifically,the power control section 90 sets the power control signal PSC active,and, receiving this, the switch circuit 114 turns on the power supplyfrom the power supply circuit 112 to the HDD 100. When the login requestis accepted, the PC1 can occupy and use the HDD 100. Therefore, byturning on the HDD 100 power on condition that the login request hascome, the data transfer (the DMA transfer) between the PC1 and the HDD100 can be conducted based on the command ORB issued by the PC1 afterhaving received the login request. Further, in the embodiment, even whenthe power switch 110 is on, unless the login request comes, the powersupply to the HDD 100 does not get turned on. Thus, according to theembodiment, during the period after the power switch 110 is turned onand until the login request comes in, the wasteful consumption ofelectricity can be avoided.

In this case, it is possible to use a technique in which the powersupply to the HDD 100 is turned “on” on condition that the BUS1 isbiased or connected. However, by this technique, the electricity isconsumed wastefully at the HDD 100 during the period after the BUS1 isbiased or disconnected until the login request comes in. In contrast, inthe present embodiment, even when the BUS1 is biased or connected,unless the login request comes, the power supply to the HDD 100 does notget turned on; therefore, it is possible to realize the power controlthat can highly effectively reduce the electricity consumption.

Further, in the embodiment, when the logout request comes from the PC1,the power supply to the HDD 100 is turned off as shown in FIG. 7(C).More specifically, the power control section 90 sets the power controlsignal PSC inactive, and, receiving this, the switch circuit 114 turnsoff the power supply from the power supply circuit 112 to the HDD 100.When the logout request is accepted, the PC1 loses its right to occupythe HDD 100 and cannot use the HDD 100 anymore. Therefore, even afterthe logout, electricity will be wastefully consumed if the HDD 100 powerstays on. In this respect, according to the embodiment, the power supplyto the HDD 100 is turned off after the logout, and, thereby, unwantedconsumption of electricity at the HDD 100 can be avoided.

Additionally, in the embodiment, even when the BUS1 is non-biased (astate in which the biased voltage is not supplied) or disconnected (astate in which the BUS1 cable is not physically connected), the powersupply to the HDD 100 is set off. As a consequence, if the PC1 issuspended and the BUS1 turns non-biased, or if the IEEE1394 cable isremoved and the BUS1 becomes turns, for example, it is possible to avoidthe unwanted consumption of electricity.

There is a technique, for example, in which the power supply the HDD 100is turned off on a single condition that the BUS1 has turned non-biasedor disconnected. However, with this technique, the power supply to theHDD 100 gets turned off only when the PC1 is suspended and the BUS 1turns non-biased or when the BUS1 cable is removed and disconnected;therefore, even when the PC1 logs out, the power supply to the HDD 100does not get turned off.

On the contrary, in the embodiment, the power supply to the HDD 100 canbe turned off as the PC1 logs out even when, for example, the PC1 is notsuspended but is at a normal state or the BUS1 cable stays connected.Therefore, it is possible to realize the power control that highlyeffectively reduces the electricity consumption. Also, according to theembodiment, the power supply to the HDD 100 can be turned off by thelogout process by the software. Therefore, with the software processalone, and without changing hardware specifications, it is possible torealize a highly flexible power control that does not consume as muchelectricity.

Now, the descriptions hereinbefore were made of the technique in whichthe power supply to the HDD 100 is turned on when the login requestcomes and is turned off when the logout request comes. However, it isnot necessary to employ the part of the technique in which the powersupply to the HDD 100 is turned off when the logout request comes, whileemploying the part in which the power supply to the HDD 100 is turned onwhen the login request comes. Alternatively, it is not necessary toemploy the part of the technique in which the power supply to the HDD100 is turned on when the login request comes, while employing the partin which the power supply to the HDD 100 is turned off when the logoutrequest comes.

3.2 Switching Control of the Data Transfer Processes

In the configuration of FIG. 6, the first data transfer control processbetween the PC1 and the HDD 100 and the second data transfer controlprocess between the PC1 and the HDD 100 can be conducted. In theembodiment, the switching control between the first and second datatransfer control processes is conducted as in the following.

To describe specifically, as shown in FIG. 8A, when the BUS1 is not inan active state and the power supply of the VBUS of the BUS3 connectedto PC2 is turned to an on state (when the voltage of the VBUS exceeds apredetermined voltage), the first data transfer control process betweenthe PC1 and the HDD 100 is switched (shifted) to the second datatransfer control process between the PC2 and the HDD 100. Note that anactive state means a state in which the BUS1 cable is physicallyconnected, the biased voltage is supplied, and it is ready to transferthe data.

Further, in the embodiment, as shown in FIG. 8A, when the first datatransfer control process is switched to the second data transfer controlprocess, the power control section 90 conducts the power control byturning off the power supply to the link layer circuit 20 (and the SBP-2circuit 22, for example) used for the first data transfer controlprocess. As a consequence, because the power supply to the link layercircuit 20 that is unused during the second data transfer controlprocess is turned off, it is possible to realize the power control thatcan highly effectively reduce the electricity consumption.

Furthermore, in the embodiment, as shown in FIG. 8B, when the BUS1 isactive and the power supply of the VBUS of the BUS3 connected to the PC2is turned off, the second data transfer control process between the PC2and the HDD 100 is switched to the first data transfer control processbetween the PC1 and the HDD 100.

By switching the data transfer control processes (data transfer paths)using the technique as described, the PC1 and the PC2 can share the HDD100, and the users' convenience can be improved. Further, the switchingcontrol can be simplified because the switching of the data transfercontrol processes can be determined only by detecting whether the BUS1is active or not or whether the VBUS is turned on or not.

Further, it is desirable that the switching between the first and thesecond data transfer control processes (the bus acquirement process) beconducted at power down when the power supply to the HDD 100 is turnedoff. More specifically, it is desirable that the switching of the datatransfer processes be carried out at power down of the HDD 100 and whenthe PC1 is not logged into the HDD 100. It is thereby possible toprevent the data transfer processes from getting switched when the PC1and PC2 are in the middle of making access to the HDD 100.

4. Process in Detail

Next, an exemplified process of the technique of the embodiment will bedescribed in detail with reference to the flowcharts of FIGS. 9 to 11.

FIG. 9 is a flowchart of the process beginning with turning on the powerand ending with completion of initialization. When the power of theapparatus (the electronic apparatus or the data transfer control IC) isturned on (step S1), a start-power-down flag and an at-power-down flag,which are inner-control variables, are set off and on, respectively(step S2).

Next, it is determined whether or not the VBUS of the USB is on (theVBUS power supply is on, or the USB cable is connected) (step S3). Then,if the VBUS is on, as described with reference to FIG. 8(B), the processmoves to the UBS process (the second data transfer process) (step S4).As a consequence, the control is handed to the USB. In contrast, if theVBUS is not on, it is determined whether or not the IEEE1394 cable isactive (biased; the IEEE 1394 cable is connected; or the data transfercontrol is possible) (step S5).

If the IEEE1394 cable is not active, the process returns to the step S3.On the other hand, if the cable is active, the bus reset is issued so asto prompt the PC1 (the host system) to log in. This means completion ofthe initialization, and, thereby, the bus reset is issued in order toprompt the PC1 to log in. Then, the process moves to the common process(the 1394 packet receiving process) (step S7). More specifically, whenthe PC1 is connected via IEEE1394, and when the PC1 has started, thereading out of the configuration ROM and the login request are carriedout, and then the process moves to the common process.

FIG. 10 is a flowchart of a process to be called when there is noprocess for the IDE (ATA, ATAPI) device (HDD) (or the IDE process iswaiting).

First, it is determined if it is logged out or the start-power-down flagis on and, also, if the at-power-down flag is off (step S11). Then, whenit is logged out and the at-power-down flag is off, or when thestart-power-down flag is on and the at-power-down flag is off, thestart-power-down flag is set off, and the at-power-down flag is set on(step S12). After that, as described with reference to FIG. 7(C), theIDE power control signal PSC is turned non-active, thereby turning off(saving) the power supply to the HDD (step S13). Thereafter, the processreturns to a main routine process (step S14).

In contrast, if, in the step S11, it is determined that it is loggedout, the start-power-down flag is off, or the at-power-down flag is on,the process then moves to the step S15. Then, it is reconfirmed whetheror not the at-power-down flag is on, and, if it is on, it is thendetermined whether or not it is logged in (steps S15 and S16). Then, ifit is logged in, as described referring to FIG. 8B, the power controlsignal PSC is turned active, and the power supply to the HDD is turnedon (step S17). Further, the at-power-down flag is brought back to off(step S18), the IDE (the HDD) is initialized (step S19), and the processgoes back to the main routine process (step S20).

In contrast, if, in the step S16, it is determined not to be in thelogin state, the process moves to the bus acquirement process (theprocess of switching the data transfer processes) (step S21). Then, itreturns to the main routine process in which the bus acquirement processends (step S22).

If, in the step S15, the at-power-down flag is determined to be not on,it is then determined whether or not the IEEE1394 bus is non-biased ordisconnected or not (step S23). Then, if it is determined that theIEEE1394 bus is non-biased or disconnected, the start-power-down flag isset on, and the process returns to the main routine process (steps S24and S25). On the contrary, if the IEEE1394 bus is determined to bebiased and connected, the process simply goes back to the main routineprocess (step S25).

After the apparatus power is turned on, for example, the at-power-downflag is set on (the step S2 of FIG. 9). Thus, in this case, the step S11moves to the steps S15 and S16 of FIG. 10. Then, if it is determined asbeing logged in in the step S16, it moves to the steps S17, S18, S19,and S20, and the power supply to the HDD is turned on while theat-power-down flag is set off. The process then returns to the mainroutine process.

Thereafter, if it is determined to be logged out, the process moves fromthe step S11 to the steps S12, S13, and S14 of FIG. 10, and the powersupply to the HDD is turned off. Then, the process returns to the mainroutine process.

In contrast, if, in the step S23, it is determined that the IEEE1394 busis non-biased or disconnected, the process moves to the steps S24 andS25, and the start-power-down flag is set on. The process therebyreturns to the main routine process. Accordingly, in the step S11,because the start-power-down flag is on thereafter, the process moves tothe steps S12, S13, and S14, and the power supply to the HDD is turnedoff. Then, the process returns to the main routine process.

FIG. 11 is a flowchart of the bus acquirement process of the step S21 ofFIG. 10. First, it is determined whether the IEEE 1394 cable is activeor not (step S31). Then, if the cable is not active, the power supply tothe link layer circuit (the SBP-2 circuit) is turned off (step S32) asdescribed with reference to FIG. 8(A). Then, until the IEEE1394 cable isturned active or until the VBUS of the USB is turned on, steps S33 andS34 are repeated. Then, if the VBUS is turned on, the process moves tothe USB process (the second data transfer process) (step S35) asdescribed in FIG. 8(A). In contrast, if the IEEE1394 cable is activated,the power supply to the link layer circuit is turned on (step S36) asdescribed in FIG. 8(B), and the process returns to a calling source (thestep S21 of FIG. 10) (step S37). That is, it returns to the IEEE1394process.

In the step. S31, if it is determined that the cable of IEEE1394 isactive, it is then determined whether or not the VBUS of the USB is on(step S38). Then, if it is on, the process moves to the USB process(step S39). In contrast, if it is not on, the process returns to thecalling source (the step S21 of FIG. 10) (step S40).

It is to be noted that the invention is not limited to the presentembodiment, and various alternative embodiments may be possible withinthe gist of the invention. For example, the terms (e.g., PC1, PC2, HDD,VBUS, IEEE1394, ATA/ATAPI, and SBP-2) used in some descriptions of thespecification and drawings and replaced with other terms (e.g., thefirst electronic apparatus, the second electronic apparatus, the device,the power line, the first interface standard, the second interfacestandard, the upper first protocol of the first interface standard) thatare broader than or synonymous with these terms can also be replacedwith the broader or synonymous terms in other descriptions in thespecification and drawings.

Further, the configuration of the data transfer control system and theelectronic apparatus is not limited to the configurations illustrated inFIGS. 5 and 6 and can be modified in various says. For example, some ofthe blocks in FIGS. 5 and 6 may be omitted, and the connections of theblocks may be altered. Furthermore, the device connected to the secondbus (BUS2) is not limited to such storage device as the HDD. Moreover,the connection configurations of the physical layer circuit, the linklayer circuit, and the data buffer are not limited to those shown inFIG. 5.

Also, in the embodiment, it is described that the management section,the power control section, and the like are operated with the firmware(program); however, part or all of these sections may be operated withthe hardware circuits.

In addition, the invention can be applied to various electronicapparatuses such as hard disc drives, optical disc drives,magnet-optical disc drives, portable information terminals, PDAs,extension equipment, audio equipment, digital video cameras, cellularphones, printers, scanners, TVs, VTRs, telephones, display devices,projection equipment, personal computers, and electronic organizers.

Moreover, in the embodiment, it is described that the invention isapplied to the data transfer based on the IEEE1394, USB, SBP-2, andATA/ATAPI standards. However, the invention can also be applied to adata transfer based on standards having similar ideas to these standardsor on standards that have been developed from these standards.

1. A data transfer control system that controls data transfer between afirst electronic apparatus connected via a first bus and a deviceconnected via a second bus, comprising: a management section thatconducts a process of receiving a login request when a login request foracquirement of a right to access to the device comes from the firstelectronic apparatus and that conducts a process of receiving a logoutrequest when a logout request for abandonment of the access rightacquired upon receipt of the login request comes from the firstelectronic apparatus; and a power control section that conducts powercontrol by turning on power supply to the device when the login requestto the device comes from the first electronic apparatus.
 2. The datatransfer system according to claim 1, wherein the power control sectionconducts power control by turning off or saving power supply to thedevice when a logout request to the device comes from the firstelectronic apparatus.
 3. The data transfer system according to claim 1,wherein the power control section conducts power control by turning offor saving power supply to the device when the first bus turns non-biasedor disconnected.
 4. The data transfer system according to claim 1,wherein a first data transfer process between the first electronicapparatus and the device is switched to a second data transfer processbetween the second electronic apparatus and the device when the firstbus is not in an active state and when power supply of a power line of athird bus that is connected to a second electronic apparatus is in an onstate.
 5. The data transfer system according to claim 4, wherein thepower control section conducts power control by turning off power supplyto a link layer circuit used for the first data transfer process whenthe first data transfer process is switched to the second data transferprocess.
 6. The data transfer system according to claim 4, wherein thesecond data transfer process is switched to the first data transferprocess when the first bus is in an active state and when power supplyof the power line of the third bus is in an off state.
 7. The datatransfer system according to claim 6, wherein the power control sectionconducts power control by turning on power supply to a link layercircuit used for the first data transfer process when the second datatransfer process is switched to the first data transfer process.
 8. Adata transfer control system that controls data transfer between a firstelectronic apparatus connected via a first bus and a device connectedvia a second bus, comprising: a management section that conducts aprocess of receiving a login request when a login request foracquirement of a right to access to the device comes from the firstelectronic apparatus and a process of receiving a logout request when alogout request for abandonment of the access right acquired upon receiptof the login request comes from the first electronic apparatus; and apower control section that conducts power control by turning off orsaving power supply to the device when the logout request to the devicecomes from the first electronic apparatus.
 9. An electronic apparatuscomprising: the data transfer system of claim 1; and the deviceconnected via the second bus.
 10. The electronic apparatus according toclaim 9, further comprising: a power switch that turns on or off powerof an electronic apparatus; a power supply circuit that supplies powerwhen the power switch is turned on; and a switch circuit, which receivesa power control signal for controlling power supply from the datatransfer control system to the device, supplies power from the powersupply circuit to the device when the power control signal turns active,and turns off or saves power supply from the power supply circuit to thedevice when the power control signal turns inactive.
 11. A program thatcontrols data transfer between a first electronic apparatus connectedvia a first bus and a device connected via a second bus, wherein theprogram makes a computer to carry out: a process of receiving a loginrequest when a login request for acquirement of a right to access to thedevice comes from the first electronic apparatus; a process of receivinga logout request when a logout request for abandonment of the accessright acquired upon receipt of the login request comes from the firstelectronic apparatus; and power control by turning on power supply tothe device when a login request to the device comes from the firstelectronic apparatus.
 12. A program that controls data transfer betweena first electronic apparatus connected via a first bus and a deviceconnected via a second bus, wherein the program makes a computer tocarry out: a process of receiving a login request when a login requestfor acquirement of a right to access to the device comes from the firstelectronic apparatus; a process of receiving a logout request when alogout request for abandonment of the access right acquired upon receiptof the login request comes from the first electronic apparatus; andpower control by turning off or saving power supply to the device when alogout request to the device comes from the first electronic apparatus.